publications
Publications by categories in reversed chronological order.
2023
- ConferenceCool-CIM: Cryogenic Operation of Analog Compute-In-Memory for Improved Power-EfficiencyIn IEEE International Electron Devices Meeting (IEDM) Dec 2023
- ConferenceCryogenic CMOS as an Enabler for Low Power Dynamic LogicIn ACM/IEEE Symposium on Low Power Electronics and Design (ISLPED) Aug 2023
2022
- ConferenceDual Temperature Memory Hierarchy and High Speed High Density Data Links for Superconducting Digital SystemsIn Applied Superconductivity Conference (ASC) Oct 2022
- JournalDesign Space Exploration of Interconnect Materials for Cryogenic Operation : Electrical and Thermal AnalysesIEEE Transactions on Ciruits and Systems I : Regular Papers Oct 2022
2021
- ConferenceMulti-bit-per-cell 1T SiGe Floating body RAM for Cache Memory in Cryogenic ComputingIn IEEE Symposium on VLSI Technology and Circuits Jul 2021
- ConferencePseudo Static 1T Capacitorless DRAM using 22nm FDSOI for Cryogenic Cache MemoryIn IEEE International Electron Devices Meeting (IEDM) Dec 2021
- JournalCharacterization and Modeling of 22nm FDSOI Cryogenic RF CMOSIEEE Journal of Exploratory Solid-State Computational Devices and Circuits Dec 2021
- JournalPerformance Analysis of Digital Standard Cells for 28nm Bulk CMOS at Cryogenic Temperature using BSIM modelsIEEE Journal of Exploratory Solid-State Computational Devices and Circuits Dec 2021
- ConferenceCryogenic RF CMOS on 22nm FDSOI Platform with Record fT=495GHz and fMAX=497GHzIn IEEE VLSI Technology Symposium Jul 2021
- JournalCryoMem: A 4K-300K 1.3GHz Hybrid 2T-Gain-Cell based eDRAM Macro in 28nm Logic Process for Cryogenic ApplicationsIEEE Solid State Circuit Letters Jul 2021
- JournalScaled Back-End Of Line Interconnects at Cryogenic TemperaturesIEEE Electron Device Letters Jul 2021
- ConferenceCryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic ApplicationsIn IEEE Custom Integrated Circuits Conference (CICC) Apr 2021
- ConferenceA 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and PerformanceIn IEEE Custom Integrated Circuits Conference (CICC) Apr 2021
- Book ChapterMultilevel Signalling for High-Speed Chiplet-to-Chiplet CommunicationIn VLSI-SoC New Technology Enabler, Springer Apr 2021
2020
- ConferenceA Model Study of Multilevel Signalling for High-Speed Chiplet-to-Chiplet Communication in 2.5D IntegrationIn Proceedings of 28th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2020) Oct 2020
2018
- ConferenceRealization of Multivalued Logic Combinational Circuits in Fully Depleted Silicon on InsulatorIn Proceedings of IEEE International Conference on Networking, Embedded and Wireless Systems Dec 2018
- ConferenceQuarternary Digital Circuits design using Carbon Nanotube FETsIn Proceedings of IEEE International Conference on Networking, Embedded and Wireless Systems Dec 2018
2016
- ConferenceTowards mitigating the impact of NBTI and PBTI DegradationIn Proceedings of 2nd World Congress on Automation and Robotics Conference Jun 2016
- JournalMitigating the impact of NBTI and PBTI DegradationGlobal Journal of Technology and Optimization Jun 2016
- Book ChapterConcluding RemarksIn Wireless Computing in Medicine: From Nano to Cloud with Ethical and Legal Implications, Wiley Jun 2016
2013
- ConferenceDesign and Implementation of Logical Cost Efficient Nanometric Fault Tolerant Reversible BCD AdderIn Proceedings of IEEE 10th INDICON Dec 2013
- ConferenceDesign of Low Logical Cost Conservative Reversible Adders using Novel PCTGIn Proceedings of IEEE 4th International Symposium on Electronic System Design Dec 2013
- ConferenceDesign of Low Logical Cost Adders using Novel Parity Conserving Toffoli GateIn Proceedings of IEEE International Conference on Emerging Trends in Communication, Control, Signal Processing and Computing Applications Oct 2013
- ConferenceTowards the Design of Fault Tolerant Reversible Circuits Components of ALU using New PCMF GateIn Proceedings of IEEE International Conference on Advances in Computing, Communication and Informatics Oct 2013
- JournalDesign of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic UnitInternational Journal of VLSI Design and Communication Systems Jun 2013
- ConferenceOptimized Reversible Vedic Multipliers for High Speed Low Power OperationsIn Proceedings of IEEE International Conference on Information and Communication Technologies Jun 2013
- ConferenceContemplation of synchronous Gray Code counter and its variants using reversible logic gatesIn Proceedings of IEEE International Conference on Information and Communication Technologies Jun 2013
- ConferenceParity preserving logic based fault tolerant reversible ALUIn Proceedings of IEEE International Conference on Information and Communication Technologies Jun 2013
- ConferenceDesign of High Speed Low Power Multiplier using Reversible logic: a Vedic Mathematical ApproachIn Proceedings of IEEE International Conference on Circuits Power and Computing Technologies Mar 2013
- JournalDesign of Fault Tolerant Reversible Multiplexer Based Multi-Boolean Function Generator using Parity Preserving GatesInternational Journal of Computer Applications Mar 2013
2012
- JournalDesign of Reversible Multipliers for Linear Filtering Applications in DSPInternational Journal of VLSI Design and Communication Systems Dec 2012
- JournalNovel Code Converter Employing Reversible LgicInternational Journal of Computer Applications Jun 2012