The 1T Capacitorless DRAM in 22nm FDSOI showing Pseudo Static behavior at low temperatures with high write endurance and non destructive read for Cryogenic Cache Applications has been accepted for IEDM-2021.

Abstract

Cryogenic CMOS processors need low latency, high bandwidth access to high-density on-die cache memory to maximize performance. In this work, we experimentally demonstrate,for the first time, pseudo-static random access memory operation of a 1T Capacitorless Floating Body DRAM using 22nm FDSOI transistor, down to 4.8K, suitable for cryogenic cache memory. We demonstrate a 1T Cryo-DRAM (W/L=120nm/20nm) that exhibit: (a) record high sensing current and sense margin (ΔIRead=IRead1-IRead0), (b) pseudo-static retention characteristics(>10^5sec); (c) high write endurance >10^10cycles, and (d) non-destructive read cycles >10^16, suitable for cache application. Benchmarking reveals that 1T Cryo-DRAM outperforms Cryo-SRAM and Cryo-STT-MRAM in memory density by 10x and 50x; in read/write energy by 2.7x/2.4x and 1.3x/1.5x and in read latency by 1.46x and 1.80x respectively for a cache size of 2MB. Hence, 1T Cryo-DRAM is a viable option for L2/L3 cache in high-performance cryogenic computing.